In a DRAM, memory cells store data in terms of electric charge. The stored charge, however, fades with time due to a leakage of current. Therefore, periodic "refresh" operations must be carried out to maintain the stored data.
If data of a high logic level is written in a DRAM cell using a low voltage, this means that the amount of the stored electric charge in a capacitor is small. Therefore, the data-holding time is limited. If the data-holding time gets too short, refreshing cannot prevent the stored data from vanishing.
5 V DRAMs of a single power source type are known from Japanese Patent Applications, published under No. 58-23386and No. 58-23387. In these prior art techniques, 6 V or 7 V, which is greater than an external power supply voltage V.sub.CC (=5 V), is used to write data into a memory cell. This prevents loss of data even if some drop in V.sub.CC occurs, thereby improving operational margins.
Another type of DRAM is disclosed by M. Aoki et al ("A 1.5 V DRAM for Battery-Based Applications", ISSCC DIGEST OF TECHNICAL PAPERS, pp.238-239, February, 1989) as well as by Japanese Patent Application, published under No. 5-21742. These prior art techniques use a cell plate voltage variation method. More specifically, the voltage of cell plates is made to vary so as to effectively boost a write voltage used to write data in a memory cell.
The above-described techniques, however, present drawbacks. In the former techniques, a high write voltage, such as 6 V or 7 V, is used. This causes the memory cell to suffer from a problem of how to resist such a high voltage, resulting in reducing DRAM life. In the latter techniques, the cell plate approach is adopted which, however, is not practical. The reason is that the capacitance of cell plates is so great that their voltage cannot be changed at high speeds.